1. Field of the Invention
Aspects of the exemplary embodiments relate a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device in which the electrical characteristics of high voltage/power devices are improved, using low voltage logic wells and a manufacturing method thereof.
2. Description of the Prior Art
As demand for small-scale multi-functional electronic devices is increasing with the development of electronic technology, System-on-a-chip (SOC) technology is introduced. SOC is a technology which integrates a plurality of electronic components having different characteristics into a single chip to implement a single system.
Modern power integrated circuits have high-voltage/power devices such as EDMOS and LDMOS integrated with low-voltage logic devices on a single chip. The process for integrating those two different types of devices on a SOC chip is very complicated and costly.
Thus, forming high voltage/power devices requires a long thermal process and additional mask steps, and the process can affect characteristics of logic devices which are used in a circuit operating at a low voltage.
Recently, in order to form high voltage/power and low voltage/logic devices through a single process, a high voltage/power device such as an extended drain metal oxide semiconductor (EDMOS) have been implemented in CMOS logic technology. Research has been conducted to replace the high voltage well of an EDMOS with the logic well of a low voltage device.
However, in case the length of the drift region near the silicon surface of EDMOS, e.g., the length of drift region between the channel region and RESUEF (Reduced Surface Electric Field) STI (Shallow Trench Isolation) is extremely short, it is very difficult to raise both breakdown voltage and device performance (speed), or to raise breakdown voltage as well as to lower the specific on-resistance.